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rev. 0.1 / mar 2009 1 this document is a general product de scription and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. h5tq2g43bmr-xxc h5tq2g83bmr-xxc 2gb ddr3 sdram ddp(1gbx2) h5tq2g43bmr-xxc h5tq2g83bmr-xxc
rev. 0.1 /mar 2009 2 h5tq2g43bmr-xxc h5tq2g83bmr-xxc revision history revision no. history draft date remark 0.1 initial release 2009-3
rev. 0.1 /mar 2009 3 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table of contents 1. description 1.1 device features and ordering information 1.1.1 description 1.1.2 features 1.1.3 ordering information 1.1.4 ordering frequency 1.2 package ball out 1.3 row and column address table: 512m/1g fixed 1.4 pin functional description 1.5 functional block diagram 2. command description 2.1 command truth table 2.2 clock enable (cke) truth table for synchronous transitions 3. absolute maximum ratings 4. operating conditions 4.1 operating temperature condition 4.2 dc operating conditions 5. ac and dc input measurement levels 5.1 ac and dc logic input levels for single-ended signals 5.2 ac and dc logic input levels for differential signals 5.3 differential input cross point voltage 5.4 slew rate definitions for single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) 5.5 slew rate definitions for differential input signals
rev. 0.1 /mar 2009 4 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels 6.1.1 differential ac and dc output levels 6.2 single ended output slew rate 6.3 differential output slew rate 6.4 reference load for ac timing and output slew rate 7. overshoot and undershoot specifications 7.1 address and control overshoot and undershoot specifications 7.2 clock, data, strobe and mask ov ershoot and undershoot specifications 7.3 34 ohm output driver dc electrical characteristics 7.4 output driver temperature and voltage sensitivity 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics 7.5.2 odt dc electrical characteristics 7.5.3 odt temperature and voltage sensitivity 7.6 odt timing definitions 7.6.1 test load for odt timings 7.6.2 odt timing reference load 8. idd specification parameters and test conditions 8.1 idd measurement conditions 8.2 idd specifications 8.2.1 idd6 current definition 8.2.2 idd6tc specification (see notes 1~2) 9. input/output capacitance 10. standard speed bins 11. electrical characteristics and ac timing 12. package dimensions
rev. 0.1 /mar 2009 5 h5tq2g43bmr-xxc h5tq2g83bmr-xxc description the h5tq2g43bmr-xxx and h5tq2g83bmr-xxx are a 2,147,483 ,648-bit cmos double data rate iii (ddr3) synchro- nous dram, ideally suited for the main memory applications which requires large memory density and high bandwidth. hynix 2gb ddr3 sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the risi ng edges of the ck (falling edges of the ck), data, data strobes and write data masks inputs are sample d on both rising and falling edges of it. the data paths are internally pipelined and 8-bi t prefetched to achieve very high bandwidth. 1.1 device features and ordering information . features ? vdd=vddq=1.5v +/- 0.075v ? fully differential clock inputs (ck, ck ) operation ? differential data strobe (dqs, dqs ) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, and (11) supported ? programmable additive latency 0, cl-1, and cl-2 supported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst length 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8banks ? 8k refresh cycles /64ms ? jedec standard 78ball fbga(x4/x8) ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? on die thermal sensor supported (jedec optional) ? 8 bit pre-fetch . ordering information * xx means binning grade (speed/idd...) * x means power consumption & temperature part no. configuration package h5tq2g43bmr-xx*x 512m x 4 78ball fbga h5tq2g83bmr-xx*x 256m x 8 . operating frequency grade frequency [mhz] remark (cl-trcd-trp) cl5 cl6 cl7 cl8 cl9 cl10 -g7 ooo ddr3-1066 7-7-7 -h9 ooooo ddr3-1333 9-9-9
rev. 0.1 /mar 2009 6 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 1.2 package ball out 1.2.1 x4 package ball out note: green nc balls indicate mechanical support balls with no internal connection 1 2 3 4 5 6 7 8 9 a vss vdd nc nc vss vdd a b vss vssq dq0 dm vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq nc dqs vdd vss vssq d e vrefdq vddq nc nc nc vddq e f odt1 vss ras ck vss cke1 f g odt0 vdd cas ck vdd cke0 g h cs1 cs0 we a10/ap zq0 zq1 h j vss ba0 ba2 a15 vrefca vss j k vdd a3 a0 a12/bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 populated ball ball not populated back view 12 a b c d e f g h j k l m n populated ball ball not populated 3 789 (top view: see the balls through the package)
rev. 0.1 /mar 2009 7 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 1.2.2 x8 package ball out note: green nc balls indicate mechanical support balls with no internal connection 1 2 3 4 5 6 7 8 9 a vss vdd nc nu/tdqs vss vdd a b vss vssq dq0 dm/tdqs vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq dq6 dqs vdd vss vssq d e vrefdq vddq dq4 dq7 dq5 vddq e f odt1 vss ras ck vss cke1 f g odt0 vdd cas ck vdd cke0 g h cs1 cs0 we a10/ap zq0 zq1 h j vss ba0 ba2 a15 vrefca vss j k vdd a3 a0 a12/bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 12 a b c d e f g h j k l m n populated ball ball not populated 3 789 (top view: see the balls through the package)
rev. 0.1 /mar 2009 8 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 1.3 row and column address table 1gb 2gb 4gb 8gb note1: page size is the number of bytes of data delive red from the array to the internal sense amplifiers when an active command is regi stered. page size is per bank, calculated as follows: page size = 2 colbits * org 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 256mb x 4 128mb x 8 64mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc a12/bc a12/bc row address a0 - a13 a0 - a13 a0 - a12 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 512mb x 4 256mb x 8 128mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc a12/bc a12/bc row address a0 - a14 a0 - a14 a0 - a13 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 1gb x 4 512mb x 8 256mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc a12/bc a12/bc row address a0 - a15 a0 - a15 a0 - a14 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 2gb x 4 1gb x 8 512mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc a12/bc a12/bc row address a0 - a15 a0 - a15 a0 - a15 column address a0 - a9, a11, a13 a0 - a9, a11 a0 - a9 page size 1 2 kb 2 kb 2 kb
rev. 0.1 /mar 2009 9 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 1.4 pin functional description input / output func tional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . cke input clock enable: cke high activates, and cke low de activates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. input buffers, excluding cke, ar e disabled during self-refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/ tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras . cas . we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location ou t of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-c ode during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during re ad/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge).a10 is sampled during a precharge command to determine whether the precharge a pplies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by bank addresses. a12 / bc input burst chop: a12 / bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst choppe d). see command truth table for details. reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low.
rev. 0.1 /mar 2009 10 dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs , dqsu, dqsu , dqsl, dqsl input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. for the x16, dqsl co rresponds to the data on dql0-dql7; dqsu corresponds to the data on dqu0-dqu7. the data strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , respectively, to provide differential pair signaling to the system during reads and wr ites. ddr3 sdram supports differential data strobe only and does not support single-ended. tdqs, tdqs output termination data strobe: tdqs/tdqs is applicable for x8 drams only. when enabled via mode register a11 = 1 in mr1, the dram wi ll enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. x4 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal electr ical connection is present. v ddq supply dq power supply: 1.5 v +/- 0.075 v v ssq supply dq ground v dd supply power supply: 1.5 v +/- 0.075 v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage zq supply reference pin for zq calibration note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function
rev. 0.1 /mar 2009 11 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 1.5 functional block diagram block diagram (ddp. 512mx4) block diagram (ddp. 256mx8) 256mx4 256mx4 clk, /ras, /cas /we, dm cke1 /cs1 odt1 cke0 /cs0 odt0 dq0~dq3 a0~a13, ba0~ba2 128mx8 128mx8 clk, /ras, /cas /we, dm cke1 /cs1 odt1 cke0 /cs0 odt0 dq0~dq7 a0~a13, ba0~ba2
rev. 0.1 /mar 2009 12 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 2. command description 2.1 command truth table (a) note 1,2,3,4 apply to the entire command truth table (b) note 5 applies to all read/write command [ba = bank address, ra = rank address, ca = column address, bc = burst chop, x = don?t care, v = valid] function abbrev iation cke cs ras cas we ba0- ba3 a13- a15 a12- bc a10- ap a0- a9, a11 notes previ ous cycle curre nt cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l hvvv vv self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h hv vv vvv vv 7,8,9,1 2 lh hh single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) wras 4 hhlhllbarfulhca write with auto precharge (bl8, on the fly) wras 8 hhlhllbarfuhhca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l lh hh vvv vv6,12 hv vv
rev. 0.1 /mar 2009 13 h5tq2g43bmr-xxc h5tq2g83bmr-xxc power down exit pdx l h lh hh vvv vv6,12 hv vv zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x notes: 1. all ddr3 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. 2. reset is low enable command which will be used only for as ynchronous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be op erated upon. for (e)mrs ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? mean s either ?defined or undefined (like floating) logic level?. 5. burst reads or writes cannot be terminated or inte rrupted and fixed/on the fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref (both vrefdq and vrefca) must be maintained during self refresh operation. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to preven t the ddr3 sdram from registering any unwanted commands between operations. a no operation command will not terminate a previous oper ation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition. function abbrev iation cke cs ras cas we ba0- ba3 a13- a15 a12- bc a10- ap a0- a9, a11 notes previ ous cycle curre nt cycle
rev. 0.1 /mar 2009 14 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 2.2 cke truth table a) notes 1-7 apply to th e entire cke truth table. b) cke low is allowed only if tmrd and tmod are satisfied. current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down l l x maintain power-down 14, 15 l h deselect or nop power-down exit 11,14 self-refresh l l x maintain self-refresh 15,16 l h deselect or nop self-refresh exit 8,12,16 bank(s) active h l deselect or nop a ctive power-down entry 11,13,14 reading h l deselect or nop power-down entry 11,13,14,17 writing h l deselect or nop pow er-down entry 11,13,14,17 precharging h l deselect or nop p ower-down entry 11,13,14,17 refreshing h l deselect or nop p recharge power-down entry 11 all banks idle h l deselect or nop precharge power-down entry 11,13,14,18 h l refresh self-refresh 9,13,18 for more details with all signals see ?2.1 command truth table? on page 12.. 10 notes: 1. cke (n) is the logic state of cke at clock edge n; ck e (n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of th e ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. 4. all states and sequences no t shown are illegal or reserved unless explic itly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt functi on is not available during self-refresh. 6. tckemin of [tbd] clocks means cke must be registered on [tbd] consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the [tbd] clocks of registration. thus, after any cke transition, cke may not transition from its vali d level during the time period of tis + [tbd] + tih. 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after txsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh can not be entered during read or wr ite operations. for a detailed list of restrictions see 8.2.1 on page 44. 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care?(including floating around vref ) in self-refresh and power-down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self-refresh operation. 17. if all banks are closed at the conclusion of the read , write or precharge command, then precharge power-down is entered, otherwise active power-down is entered. 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, and all timings from previous operatio ns are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc . ) as well as all self-refresh exit and power-down exit parameters are satisfied (txs, txp, txpdll, etc).
rev. 0.1 /mar 2009 15 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 3. absolute maximum ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v ,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v ,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 , 2 notes: 1. stresses greater than those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operatio n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv.
rev. 0.1 /mar 2009 16 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 4. operating conditions 4.1 operating temperature condition 4.2 recommended dc operating conditions symbol parameter rating units notes toper operating temperature (tcase) 0 to 85 o c 2 extended temperature range 85 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatur es where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for so me devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended te mperature range. please refer to supplier data sheet and/or the dimm spd for option availability. b) if self-refresh operation is required in the ex tended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters ar e measured with vdd and vddq tied together.
rev. 0.1 /mar 2009 17 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 5. ac and dc inpu t measurement levels 5.1 ac and dc logic input leve ls for single-ended signals the dc-tolerance limits and ac -noise limits for the refere nce voltages vrefca and vrefdq are illustrated in below figure. it shows a valid reference voltage vref (t ) as a function of time. (vref stands for vrefca and vrefdq likewise). vref (dc) is the linear average of vref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. furthermore vref (t) may temporarily deviate from vref (dc) by no more than +/- 1% vdd. illustration of vref (dc) to lerance and vref ac-noise limits single ended ac and dc input levels symbol parameter ddr3-1066, ddr3-1333 unit notes min max vih(dc) dc input logic high vref + 0.100 tbd v 1 vil(dc) dc input logic low tbd vref - 0.100 v 1 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 v refdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 v refca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd notes: 1. for dq and dm, vref = vrefdq. for input any pins except reset , vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.1 /mar 2009 18 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 5.2 ac and dc logic input leve ls for differential signals note1. refer to ?overshoot and undershoot specification on page 25? 5.3 differential inpu t cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements below table. the differential input cross point voltage vi x is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vix definition cross point voltage for differ ential input signals (ck, dqs) symbol parameter ddr3-1066, ddr3-1333 unit notes min max vihdiff differential inpu t logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 symbol parameter ddr3-1066, ddr3-1333 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 150 mv vdd vss vdd/2 v ix v ix v ix ck , dqs ck, dqs
rev. 0.1 /mar 2009 19 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 5.4 slew rate definitions fo r single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih (ac) min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil (ac) max. 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising sign al is defined as the slew rate betw een the last crossing of vil (dc) max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih ( dc) min and the first crossing of vref. single-ended input sl ew rate definition input nominal slew rate defi nition for single-ended signals description measured defined by applicable for min max input slew rate for rising edge vref vih (ac) min vih (ac) min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil (ac) max vref-vil (ac) max delta tfs input slew rate for rising edge vil (dc) max vref vref-vil (dc) max delta tfh hold (tih, tdh) input slew rate for falling edge vih (dc) min vref vih (dc) min-vref delta trh delta tfs delta trs vih(ac)m in vih (dc)m in vih (dc)m ax vih(ac)m ax vrefd q or vrefca part a: set up single ended input voltage(dq,add, cmd) part b: hold delta tfh delta trh vih (ac)m in vih (d c)m in vih (d c)m ax vih (ac)m ax vrefd q or vrefca single ended input voltage(dq,add, cmd) figure 82 in p u t n o m in a l s le w r a te d e fin itio n fo r s in g le -e n d e d s ig n a ls
rev. 0.1 /mar 2009 20 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 5.5 slew rate definitions fo r differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in table and figure . note: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck#
rev. 0.1 /mar 2009 21 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels table shows the output levels used for measurements of single ended signals. 6.1.1 differential ac and dc output levels below table shows the output levels used for measurements of differential signals. 6.2 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and vo h(ac) for single ended signals as shown in table and figure. note: output slew rate is verified by design and characte rization, and may not be subject to production test. symbol parameter ddr3-1066, 1333 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of ? 1 x vddq is based on approximately 50% of the stat ic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. symbol parameter ddr3-1066, 1333 unit notes vohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 1. the swing of ? x vddq is based on approximately 50% of the stat ic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse
rev. 0.1 /mar 2009 22 h5tq2g43bmr-xxc h5tq2g83bmr-xxc fig. single ended output slew rate definition parameter symbol ddr3-1066 ddr3-1333 units min max min max single-ended output slew rate srqse 2.5 5 2.5 5 v/ns delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq) single ended output slew rate definition table. output slew rate (single-ended) *** for ron = rzq/7 setting
rev. 0.1 /mar 2009 23 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 6.3 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff (ac) and vohdiff (ac) for differential signals as shown in table and figure . differential output slew rate definition note: output slew rate is verified by design and characte rization, and may not be subject to production test. fig. differential output slew rate definition table. differential output slew rate ***for ron = rzq/7 setting description measured defined by from to differential output slew rate for rising edge voldiff (ac) vohdiff (ac) vohdiff (ac)-voldiff (ac) deltatrdiff differential output slew rate for falling edge vohdiff (ac) voldiff (ac) vohdiff (ac)-voldiff (ac) deltatfdiff parameter symbol ddr3-1066 ddr3-1333 units min max min max differential output slew rate srqdiff 5 10 5 10 v/ns delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition
rev. 0.1 /mar 2009 24 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 6.4 reference load for ac ti ming and output slew rate figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particul ar system environment or a depiction of the actual load pre- sented by a production tester. system desi gners should use ibis or ot her simulation tools to correlate the timing reference load to a system environment. manufactur ers correlate to their production test co nditions, generally one or more coaxial transmission lines terminated at the tester electronics. dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck reference load for ac timing and output slew rate
rev. 0.1 /mar 2009 25 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 7. overshoot and undershoot specifications 7.1 address and control overshoot and undershoot specifications table. ac overshoot/under shoot specification for address and control pins description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.5 v-ns 0.4 v-ns maximum undershoot area below vss (see figure) 0.5 v-ns 0.4 v-ns m axim um am plitude overshoot area vdd vss maximum amplitude undershoot area time (ns) address and control overshoot and undershoot definition
rev. 0.1 /mar 2009 26 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 7.2 clock, data, strobe and mask overshoot and un dershoot specifications table. ac overshoot/undersh oot specification for clock, data, strobe and mask description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for un dershoot area (see figure) 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.19 v-ns 0.15 v-ns maximum undershoot area below vssq (see figure) 0.19 v-ns 0.15 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.1 /mar 2009 27 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 7.3 34 ohm output driver dc electrical characteristics a functional representation of the output buffer is show n in figure . output driver impedance ron is defined by the value of the external reference resistor rzq as follows: ron34 = rzq / 7 (nominal 34.3 w 10 % with nominal rzq = 240 w 1%) the individual pull-up and pull-down resistor s (ronpu and ronpd) are defined as follows: under the condition that ronpd is turned off under the condition that ronpu is turned off ron pu v ddq v out ? i out -------------------- ------------------ = ron pd v out i out -------------- - = to other circuitry like rcv, ... ipu ronpu ronpd ipd output driver iout vout vssq dq vddq chip in drive mode output driver: definition of voltages and currents
rev. 0.1 /mar 2009 28 h5tq2g43bmr-xxc h5tq2g83bmr-xxc notes: 1. the tolerance limits are specified af ter calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the lineari ty spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd, both at 0.5 x vddq: 7.4 output driver temperature and voltage sensitivity if temperature and/or voltage change af ter calibration, the tolerance limits widen according to table and table . dt = t - t (@calibration); dv= vddq - vddq (@calibration); vdd = vddq drondt and drondv are not subject to production te st but are verified by design and characterization. output driver dc electrical characteristics, assuming r zq =240 ? ; entire operating temperature range; after proper zq calibration ron nom resistor v out min nom max unit notes 34 ? ron 34pd v oldc = 0.2 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 ron 34pu v oldc = 0.2 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 mismatch between pull-up and pull-down, mm pupd v omdc 0.5 v ddq -10 +10 % 1, 2, 4 output driver sensitivity definition min max unit ronpu@ v ohdc 0.6 - dr on dth*| ? t| - dr on dvh*| ? v| 1.1 + dr on dth*| ? t| + dr on dvh*| ? v| rzq/7 ron@ v omdc 0.9 - dr on dtm*| ? t| - dr on dvm*| ? v| 1.1 + dr on dtm*| ? t| + dr on dvm*| ? v| rzq/7 ronpd@ v oldc 0.6 - dr on dtl*| ? t| - dr on dvl*| ? v| 1.1 + dr on dtl*| ? t| + dr on dvl*| ? v| rzq/7 output driver voltage an d temperature sensitivity min max unit dr on dtm 0 1.5 %/ o c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/ o c dr on dvl 0 tbd %/mv mm pupd ron pu ron pd ? ron nom ---------------- ----------------- ---------------- y 100 =
rev. 0.1 /mar 2009 29 h5tq2g43bmr-xxc h5tq2g83bmr-xxc these parameters may not be subject to production te st. they are verified by design and characterization. 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defined by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs and tdqs/tdqs (x8 devices only) pins. a functional representation of the on-die termination is sh own in figure . the individual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows: under the condition that rttpd is turned off under the condition that rttpu is turned off dr on dth 01.5 %/ o c dr on dvh 0tbd%/mv output driver voltage an d temperature sensitivity min max unit 355 1v 7 %%2 7 0vu ? * 0vu ------------------- -------------- = 355 1e 7 0vu * 0vu ------------ - = to other circuitry like rcv, ... ipu rttpu rttpd ipd odt iout vout vssq dq vddq c h ip in t e rm in a tio n m o d e o n-d ie term ination : d efinition of voltages and currents iout = ipd-ipu io_ctt_definition_01
rev. 0.1 /mar 2009 30 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 7.5.2 odt dc electrical characteristics a below table provides an overview of the odt dc electrical characteristics. the values for rtt60pd120, rtt60pu120, rtt120pd240, rtt120pu240, rtt40pd80, rt t40pu80, rtt30pd60, rtt30pu60, rt t20pd40, rtt20pu40 are not specifi- cation requirements, but can be used as design guide lines: odt dc electrical characteristics, assuming r zq =240 ? +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes 0, 1, 0 120 ? rtt 120pd240 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) rtt 120pu240 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) rtt 120 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /2 1) 2) 5) 0, 0, 1 60 ? rtt 60pd120 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) rtt 60pu120 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) rtt 60 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /4 1) 2) 5)
rev. 0.1 /mar 2009 31 h5tq2g43bmr-xxc h5tq2g83bmr-xxc the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. pull-down and pull-up odt resistors are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. not a specification requiremen t, but a design guide line. measurement definition for rtt: 0, 1, 1 40 ? rtt 40pd80 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) rtt 40pu80 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) rtt 40 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /6 1) 2) 5) 1, 0, 1 30 ? rtt 30pd60 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) rtt 30pu60 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) rtt 30 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /8 1) 2) 5) 1, 0, 0 20 ? rtt 20pd40 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) rtt 20pu40 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) rtt 20 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /12 1) 2) 5) deviation of v m w.r.t. v ddq /2, d v m -5 +5 % 1) 2) 5) 6) odt dc electrical characteristics, assuming r zq =240 ? +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes
rev. 0.1 /mar 2009 32 h5tq2g43bmr-xxc h5tq2g83bmr-xxc apply vih (ac) to pin under test and measure current i(vih (a c)), then apply vil (ac) to pin under test and measure cur- rent i(vil (ac)) respectively. measurement definition for vm and dvm: measure voltage (vm) at test pin (midpoint) with no load: 7.5.3 odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table and table . dt = t - t (@calibration); dv= vddq - vddq (@calibration); vdd = vddq these parameters may not be subject to production te st. they are verified by design and characterization odt sensitivity definition min max unit rtt 0.9 - dr tt dt*| ? t| - dr tt dv*| ? v| 1.6 + dr tt dt*| ? t| + dr tt dv*| ? v| rzq/2,4,6,8,12 odt voltage and temperature sensitivity min max unit dr tt dt 0 1.5 %/ o c dr tt dv 0 0.15 %/mv rtt v ih(ac) v il(ac) ? i (vih(ac)) i (vil(ac)) ? ---------------------------------- ----------------------- = v m ? 2 v m ? v ddq ----------------- -1 ? ?? ?? 100 ? =
rev. 0.1 /mar 2009 33 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 7.6 odt timing definitions 7.6.1 test load for odt timings different than for timing measurements, the refere nce load for odt timings is defined in figure . 7.6.2 odt timing reference load odt timing definitions definitions for taon, taonpd, taof, taofpd and tadc are pr ovided in the table and subs equent figures. measurement reference settings are provided in the table. odt timing definitions symbol begin point definition end point definition figure t aon rising edge of ck - ck defined by the end point of odtlon extrapolated po int at vssq figure t aonpd rising edge of ck - ck with odt being first registered high extrapolated po int at vssq figure t aof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure t aofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom figure t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq /12 r zq /2 0.20 0.30 bd_refload_odt ck ck, vddq dqs dqs, tdqs tdqs, dq, dm dut vtt = vssq rtt = 25 ? vssq timing reference points
rev. 0.1 /mar 2009 34 h5tq2g43bmr-xxc h5tq2g83bmr-xxc definition of taon definition of taonpd ck ck vtt td_taon_def t aon vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtlon v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2 ck ck vtt td_taonpd_def t aonpd vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered high v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2
rev. 0.1 /mar 2009 35 h5tq2g43bmr-xxc h5tq2g83bmr-xxc definition of taof definition of taofpd ck ck vtt td_taof_def t aof dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2 ck ck vtt td_taofpd_def t aofpd dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2
rev. 0.1 /mar 2009 36 h5tq2g43bmr-xxc h5tq2g83bmr-xxc definition of tadc ck ck td_tadc_def t adc dqs dq, dm dqs, tdqs tdqs, v sw1 v sw2 end point: extrapolated point at vrtt_nom t sw11 t sw21 t adc end point: extrapolated point at vrtt_wr vtt vssq vrtt_nom vrtt_wr vrtt_nom t sw12 t sw22 begin point: rising edge of ck - ck defined by the end point of odtlcnw begin point: rising edge of ck - ck defined by the end point of odtlcwn4 or odtlcwn8
rev. 0.1 /mar 2009 37 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 8. idd and iddq spec ification parameters and test conditions 8.1 idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt, i dd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) are measured as time-averaged curren ts with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied together. any idd current is not included in iddq currents. attention: iddq values cannot be direct ly used to calculate io power of the ddr3 sdram. they can be used to sup- port correlation of simulated io power to actual io power as ou tlined in figure 2. in dra m module application, iddq cannot be measured separately since vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?floating? is defined as inputs are vref - vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1 on page 39. ? basic idd and iddq measurement conditions are described in table 2 on page 42. ? detailed idd and iddq measurement-loop patterns are desc ribed in table 3 on page 42 through table 10 on page 47. ? idd measurements are done after properly initializing the ddr 3 sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (4 0 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement -loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} ?define d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 0.1 /mar 2009 38 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load co ndition may be different from above] figure 2 - correlation from simulated channel io power to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.1 /mar 2009 39 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 unit 7-7-7 9-9-9 t ck 1.875 1.5 ns cl 7 9 nck n rcd 79nck n rc 27 33 nck n ras 20 24 nck n rp 79nck n faw x4/x820 20nck x16 27 30 nck n rrd x4/x8 4 4 nck x16 6 5 nck n rfc -512mb 48 60 nck n rfc -1 gb 59 74 nck n rfc - 2 gb 86 107 nck n rfc - 4 gb 160 200 nck n rfc - 8 gb 187 234 nck symbol description i dd0 operating one bank ac tive-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partially toggling according to table 3 on page 42; data io: floating; dm: stable at 0; bank activity: cycling with one bank ac tive at a time: 0,0,1,1,2,2,... (see table 3 on page 42); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3 on page 42 i dd1 operating one bank ac tive-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank addr ess inputs, data io: partially toggling according to table 4 on page 43; dm: stable at 0; bank activity: cycl ing with on bank active at a time: 0,0,1,1,2,2,... (see table 4 on page 43); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4 page 43 i dd2n precharge standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 5 on page 44; data io: floating; dm: stable at 0; bank activity: all banks closed; outp ut buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 44
rev. 0.1 /mar 2009 40 h5tq2g43bmr-xxc h5tq2g83bmr-xxc i dd2nt precharge standby odt current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 6 on page 44; data io: floating; dm: stable at 0; bank activity: all banks closed; outp ut buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6 on page 44; pattern details: see table 6 on page 44 i ddq2nt (optional) precharge standby odt iddq current same definition like for idd2nt, however meas uring iddq current instead of idd current i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 5 on page 44; data io: floating; dm: stable at 0; bank activity: all banks open; out put buffer and rtt: e nabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 44 i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floa ting; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i ddq4r (optional) operating burst read iddq current same definition like for idd4r, however meas uring iddq current instead of idd current
rev. 0.1 /mar 2009 41 h5tq2g43bmr-xxc h5tq2g83bmr-xxc i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between rd; com- mand, address, bank address inputs: partially toggli ng according to table 7 on page 45; data io: seamless read data burst with different data bet ween one burst and the next one according to table 7 on page 45; dm: stable at 0; bank activity: all banks open, rd command s cycling through banks: 0,0, 1,1,2,2,...(see table 7 on page 45); output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7 on page 45 i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between wr; com- mand, address, bank address inputs: partially toggli ng according to table 8 on page 45; data io: seamless read data burst with different data bet ween one burst and the next one according to table 8 on page 45; dm: stable at 0; bank activity: all banks open, wr comma nds cycling through banks: 0,0,1,1,2,2,...(see table 8 on page 45); output buffer and rt t: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8 on page 45 i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1 on page 38; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partially togg ling according to table 9 on page 45; data io: float- ing; dm: stable at 0; bank activity: ref command ev ery nref (see table 9 on page 45); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9 on page 45 i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 4; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6et self-refresh current: extended temperature range (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 4; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm : stable at 0; bank acti vity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6tc auto self-refresh current (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm: stable at 0; bank activity: auto self-refresh opera- tion; output buffer and rtt: enabled in mode registers b) ; odt signal: floating
rev. 0.1 /mar 2009 42 h5tq2g43bmr-xxc h5tq2g83bmr-xxc a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) refer to dram supplier data sheet and/ or dimm spd to determine if optional fe atures or requirements are supported by ddr3 sdram device table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1 on page 39; bl: 8 a) ; al: cl-1; cs : high between act and rda; command, address, bank address inputs: partially toggling according to table 10 on page 47; data io: read data burst with different data between one burst and the next one according to table 10 on page 47; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10 on page 47; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10 on page 47 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 00 00 0 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 /mar 2009 43 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, trun cate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 /mar 2009 44 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. table 6 - idd2nt and iddq2nt measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 10000000000 - 1 d 1000000 0 0 00 - 2d 111100000f0 - 3d 111100000f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1 1 1 1 0 0 0 0 0 f 0 00000000 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.1 /mar 2009 45 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 7 - idd4r and iddq24rmeasurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise floating. b) burst sequence driven on each dq signal by write command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.1 /mar 2009 46 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.1 /mar 2009 47 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 10 - idd7 measurement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd ... d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-lo op 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-lo op 1, but ba[2:0] = 7 9 nfaw+4*nrrd ... d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 14 3*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 0.1 /mar 2009 48 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 8.2 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. i dd specification speed grade bin ddr3 - 1066 7-7-7 ddr3 - 1333 9-9-9 unit notes symbol max. max. i dd0 150 165 ma x4/x8 i dd1 170 180 ma x4/x8 i dd2n 120 130 ma x4/x8 i dd2nt 130 140 ma x4/x8 i ddq2nt 140 140 ma x4 160 160 ma x8 i dd2p0 20 20 ma x4/x8 i dd2p1 56 60 ma x4/x8 i dd2q 120 140 ma x4/x8 i dd3n 140 160 ma x4/x8 i dd3p 80 80 ma x4/x8 i dd4r 215 245 ma x4/x8 i ddq4r 120 125 ma x4/x8 i dd4w 220 255 ma x4/x8 i dd5b 260 275 ma x4/x8 i dd6 20 20 ma x4/x8 i dd6et 24 24 ma x4/x8 i dd6tc 24 24 ma x4/x8 i dd7 280 325 ma x4 290 335 ma x8
rev. 0.1 /mar 2009 49 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 9. input/output capacitance ddr3-1066 ddr3-1333 parameter symbol min max min max units notes input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io tbd tbd tbd tbd pf 1,2,3 input capacitance, ck and ck c ck tbd tbd tbd tbd pf 2,3 input capacitance delta ck and ck c dck tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs c ddqs tbd tbd tbd tbd pf 2,3,5 input capacitance delta (all ctrl input-only pins) c di_ctrl tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd tbd tbd tbd tbd pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs ) c dio tbd tbd tbd tbd pf 2,3,11 notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to prod uction test. it is verified by design and characterization. the capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to mono lithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck . 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras , cas , we . 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk )) 9. add pins defined as a0-a15, ba0- ba2 and cmd pins are defined as ras , cas and we . 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk )) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs ))
rev. 0.1 /mar 2009 50 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 10. standard speed bins ddr3 sdram standard speed bins include tck, trcd, trp, tras and trc for each corresponding bin. ddr3-1066 speed bins for specific notes see ?? on page 51. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3) supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck
rev. 0.1 /mar 2009 51 h5tq2g43bmr-xxc h5tq2g83bmr-xxc ddr3-1333 speed bins for specific notes see ?? on page 51.. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 20 ns act to internal read or write delay time t rcd 13.5 ? ns pre command period t rp 13.5 ? ns act to act or ref command period t rc 49.5 ? ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6, 8, 9 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.1 /mar 2009 52 h5tq2g43bmr-xxc h5tq2g83bmr-xxc speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl sett ing result in tck(avg).min and tck(avg).max requirements. when ma king a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed . an application should use the next smaller jedec standard tck (avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calcul ating cl [nck] = taa [ns] / tck (avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck (avg) = taa.max / cl selected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck( avg).max corresponding to clse lected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and spd in formation if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 8. any ddr3-1600 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 11. electrical characte ristics and ac timing timing parameters by speed bin note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8-8-ns6 average clock period tck (avg) ps f average high pulse width tch (avg) 0.47 0.53 0.47 0.53 tck (avg) f average low pulse width tcl (avg) 0.47 0.53 0.47 0.53 tck (avg) f absolute clock period tck (abs) tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max ps absolute clock high pulse width tch (abs) 0.43 - 0.43 - tck (avg) 25 absolute clock low pulse width tcl (abs) 0.43 - 0.43 - tck (avg) 26 clock period jitter jit (per) - 90 90 - 80 80 ps
rev. 0.1 /mar 2009 53 h5tq2g43bmr-xxc h5tq2g83bmr-xxc clock period jitter during dll locking period tjit (per, lck) - 80 80 - 70 70 ps cycle to c ycle period jitter tjit (cc) 180 160 ps cycle to c ycle period jitter during dll locking period tjit (cc, lck) 160 140 ps duty cycle jitter tjit (duty) ----ps cumulative error across 2 cycles terr (2per) -132 132 -118 118 ps cumulative error across 3 cycles terr (3per) -157 157 -140 140 ps cumulative error across 4 cycles terr (4per) -175 175 -155 155 ps cumulative error across 5 cycles terr (5per) -188 188 -168 168 ps cumulative error across 6 cycles terr (6per) -200 200 -177 177 ps cumulative error across 7 cycles terr (7per) -209 209 -186 186 ps cumulative error across 8 cycles terr (8per) -217 217 -193 193 ps cumulative error across 9 cycles terr (9per) -224 224 -200 200 ps cumulative error across 10 cycles terr (10per) -231 231 -205 205 ps cumulative error across 11 cycles terr (11per) -237 237 -210 210 ps cumulative error across 12 cycles terr (12per) -242 242 -215 215 ps cumulative error across n = 13, 14,.....49, 50 cycles terr (nper) ps 24 data timing dqs, dqs to dq skew, per group, per access tdqsq - 150 - 125 ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - tck (avg) 13, b dq low-impedance time from ck, ck tlz (dq) - 600 300 - 500 250 ps 13, 14, a dq high impedance time from ck, ck thz (dq) - 300 - 250 ps 13, 14, a timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 54 h5tq2g43bmr-xxc h5tq2g83bmr-xxc data setup time to dqs, dqs referenced to vih (ac) / vil (ac) levels tds (base) 25 tbd ps d, 17 data hold time from dqs, dqs referenced to vih (dc) / vil (dc) levels tdh (base) 100 tbd ps d, 17 data strobe timing dqs,dqs differential read preamble trpre 0.9 note 0.9 note tck (avg) 13, 19 b dqs, dqs differential read postamble trpst 0.3 note 0.3 note tck (avg) 11, 13, b dqs, dqs differential output high time tqsh 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential output low time tqsl 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential write preamble twpre 0.9 - 0.9 - tck (avg) dqs, dqs differential write postamble twpst 0.3 - 0.3 - tck (avg) dqs, dqs rising edge output access time from rising ck, ck tdqsck - 300 300 - 255 255 ps 13, a dqs and dqs low- impedance time (referenced from rl - 1) tlz(dqs) - 600 300 - 500 250 ps 13, 14, a dqs and dqs high- impedance time (referenced from rl + bl/2) thz(dqs) - 300 - 250 ps 13, 14 a dqs, dqs differential input low pulse width tdqsl 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs differential input high pulse width tdqsh 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs rising edge to ck, ck rising edge tdqss - 0.25 0.25 - 0.25 0.25 tck (avg) c timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 55 h5tq2g43bmr-xxc h5tq2g83bmr-xxc dqs, dqs falling edge setup time to ck, ck rising edge tdss 0.2 - 0.2 - tck (avg) c dqs, dqs falling edge hold time from ck, ck rising edge tdsh 0.2 - 0.2 - tck (avg) c command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp max (4nck, 7.5ns) - max (4nck, 7.5ns) -e delay from start of internal write transaction to internal read command twtr max (4nck, 7.5ns) - max (4nck, 7.5ns) -e, 18 write recovery time twr 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod max (12nck , 15ns) - max (12nck , 15ns) - act to internal read or write delay time trcd e pre command period trp e act to act or ref command period trc e cas to cas command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal (min) nck end of mpr read burst to msr for mpr (exit) tmprr 1 - 1 - nck 22 active to precharge command period tras e active to active command period for 1kb page size trrd max (4nck , 7.5ns) - max (4nck, 6ns) -e active to active command period for 2kb page size trrd max (4nck, 10ns) - max (4nck, 7.5ns) -e four activate window for 1kb page size tfaw 37.5 - 30 - ns e timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 56 h5tq2g43bmr-xxc h5tq2g83bmr-xxc four activate window for 2kb page size tfaw 50 - 45 - ns e command and address setup time to ck, ck referenced to vih (ac) / vil (ac) levels tis (base) 125 65 ps b, 16 command and address hold time from ck, ck referenced to vih (dc) / vil (dc) levels tih (base) 200 140 ps b, 16 command and address setup time to ck, ck referenced to vih (ac) / vil (ac) levels tis (base) ac150 --65+125 ps b, 16, 27 calibration timing power-up and reset calibration time tzqinit 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - self refresh timings exit self refresh to commands not requiring a locked dll txs max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk (min) - tdllk (min) -nck minimum cke low width for self refresh entry to exit timing tckesr tcke (min) + 1 nck - tcke (min) + 1 nck - valid clock requirement after self refresh entry (sre) or power- down entry (pde) tcksre max (5 nck, 10 ns) - max (5 nck, 10 ns) - timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 57 h5tq2g43bmr-xxc h5tq2g83bmr-xxc valid clock requirement before self refresh exit (srx) or power- down exit (pdx) or reset exit tcksrx max (5 nck, 10 ns) - max (5 nck, 10 ns) - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3nck, 7.5ns) - max (3nck, 6ns) - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max (10nck, 24ns) - max (10nck, 24ns) -2 cke minimum pulse width tcke max (3nck, 5.625ns) - max (3nck, 5.625ns) - command pass disable delay tcpded 1 - 1 - nck power down entry to exit timing tpd tcke (min) 9 * trefi tcke (min) 9 * trefi 15 timing of act command to power down entry tactpden 1 - 1 - nck timing of pre or prea command to power down entry tprpden 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl + 4 + 1 - rl + 4 + 1 - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl + (twr / tck (avg)) - wl+4 + (twr / tck (avg)) -nck9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl+4+ wr+ 1 - wl+4 + wr + 1 - nck 10 timing of wr command to power down entry (bc4mrs) twrpden wl+2+ (twr / tck (avg)) - wl+2 + (twr / tck (avg)) -nck9 timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 58 h5tq2g43bmr-xxc h5tq2g83bmr-xxc timing of wra command to power down entry (bc4mrs) twrapden wl + 2 + wr + 1 - wl + 2 + wr + 1 - nck 10 timing of ref command to power down entry trefpden 1 - 1 - nck , timing of mrs command to power down entry tmrspden tmod (min) - tmod (min) - odt timings odt high time without write command or with write command and bc4 odth4 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 1 9 1 9 ns asynchronous rtt turn-off delay (power- down with dll fro- zen) taofpd 1 9 1 9 ns rtt turn-on taon -300 300 -250 250 ps 7, a rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck (avg) 8, a rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck (avg) a write leveling timings first dqs/dqs rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck 3 dqs/dqs delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 245 - 195 - ps timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 59 h5tq2g43bmr-xxc h5tq2g83bmr-xxc write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 245 - 195 - ps write leveling output delay twlo 0 9 0 9 ns write leveling output error twloe 0 2 0 2 ns timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-1066 ddr3-1333 parameter symbol min max min max units notes
rev. 0.1 /mar 2009 60 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 0.1 jitter notes specific note a when the device is op erated with input clock jitter, this parameter needs to be derated by the actual terr (mper), act of the input clock, where 2 <= m <=12.(output deratings are relative to the sdram input cl ock.) for example, if the measured jitter into a ddr-800 sdram has terr (mper), act, min = -172 ps and terr (mper), act, max =+ 193 ps, then t dqsck, min (derated) = tdqsck, min - terr (mper), act, max = -400 ps - 193 ps = - 593 ps and tdqsck, max (derated) = tdqsck , max - terr (mper), act, min = 400 ps+ 172 ps = + 572 ps. similarly, tlz (dq) for ddr3-800 derates to tlz (dq), min (derated) = - 800 ps - 193 ps = - 993 ps and tlz (dq), max (derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr (mper), act, min is the minimum mea- sured value of terr (nper) where 2 <= n <=12 , and terr (mper), act, max is the maxi- mum measured value of terr (nper) where 2 <= n <= 12 specific note b when the device is op erated with input clock jitter, this parameter needs to be derated by the actual tjit (per), act of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has tck (avg), act = 2500 ps, tjit (per), act, min = - 72 ps and tjit (per), act, max = + 93 ps, then trpre, min (derated) = trpre, min + tjit (per), act, min = 0.9 x tck (avg), act + tjit (per), act, min (derated) = trpre, min + tjit ( per), act, min = 0.9 x tck (avg), act + tjit (per), act, min = 0.9 x 2500 ps - 72 ps =+ 2178 ps. similarly, tqh, min (derated) = tqh, min + tjit (per), act, min = 0.38 x tck (avg), act + tjit (per), act, min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs(l/u) ) cross- ing to its respective clock signal (ck, ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit (per), tjit (cc), etc. ), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective da ta strobe signal (dqs(l/u), dqs(l/u) ) crossing. specific note e for these parameters, the dd r3 sdram device supports tnparam [nck] = ru {tparam [ns] / tck (avg) [ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the de vice will support tnrp = ru {trp / tck (avg)}, which is in clock cycles , if all input clock jitter specif ications are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, th e device will support tnrp = ru {trp / tck (avg)} = 6, as long as the i nput clock jitter specif ications are met, i. e. precharge command at tm and active command at tm+6 is valid ev en if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous tim- ing holds at all times. (min and max of spec values are to be used fo r calculations in ta b l e .
rev. 0.1 /mar 2009 61 h5tq2g43bmr-xxc h5tq2g83bmr-xxc timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rounded-up to next higher integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see 4.2.2 ?timing parameters? on page 93. 8. for definition of rtt turn-off time taof see 4.2.2 ?timing parameters? on page 93. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0. 11. the maximum postamble is bound by thzdqs (max) 12. output timing derati ngs are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by t.b.d. 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter for definition and measurement method. 15. trefi depends on toper 16. tis (base) and tih (base) values are for 1v/n s cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, vref(dc) = vrefdq (dc). for input only pins except reset , vref (dc) = vrefca (dc). see ?address / command setup, hold and derating? on page 62. 17. tds (base) and tdh (base) values are for 1v/n s dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, vref(dc) = vrefdq (dc). for input only pins except reset , vref (dc) = vrefca (dc). see ?data setup, hold and slew rate derating? on page 70.. 18. start of internal write transa ction is definited as follows: for bl8 (fixed by mrs and on- the-fly): rising clock edge 4 clock cycles after wl. for bc4 (on- the- fly): rising cl ock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising cl ock edge 2 clock cycles after wl. 19. the maximum preamble is bound by tlzdqs (min) 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a re fresh command once trefpden (m in) is satisfied, there are cases where additional time su ch as txpdll (min) is also required. 22. defined between end of mpr read burst and mr s which reloads mpr or disables mpr function. 23. one zqcs command can effectively co rrect a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temper ature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and ot her application specific paramete rs. one method for calculating the interval between zqcs comma nds, given the temperature (tdrifrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the ap plication, is illustrated. the interval could be defined by the following formula.
rev. 0.1 /mar 2009 62 h5tq2g43bmr-xxc h5tq2g83bmr-xxc where tsens = max (drttdt, drondtm) and vsens = max (drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / o c, vsens = 0.15% / mv, tdriftrate = 1 o c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 24. n = from 13 cycles to 50 cycles. 25. tch (abs) is the absolute instantaneou s clock high pulse width, as measured fr om one rising edge to the following fall ing edge. 26. tcl (abs) is the absolute instantaneou s clock low pulse width, as measured from one falling edge to the following ris ing edge. 27. the tis (base) ac150 specifications are adjusted from the tis (base) specification by adding an additional 100 ps of derating to accommodate for the lower al ternate threshold of 150 mv and another 25 ps to account for the earlier refer ence point [(175 mv - 150 mv) / 1 v/ns]. address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis (base) and tih (base) value (see table 1) to the ? tis and ? tih derating value (see table 2) respectively. example: tis (total setup time) = tis (base) + ? tis setup (tis) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil (ac) max. if the actual signal is alwa ys earlier than the nominal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for deratin g value (see figure 2). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc leve l is used for derating value (see figure 4). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil (dc) max and the first crossing of v ref(dc) . hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last cross- ing of vih (dc) min and the first crossing of v ref(dc) . if the actual signal is always late r than the nominal slew rate line between shaded ?dc to v ref(dc) region?, use nominal slew rate for derating va lue (see figure 3). if the actual signal is ear- lier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 4). for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac (see table 4). zqcorrection (tsens x tdriftrate)+ ( vsens x vdriftrate) -------------------------- ------------------------------ ----------------------------- ----------------------- 0.5 (1.5 x 1)+(0.15 x 15) ------------------------------- ----------------------- 0 . 1 3 3 1 2 8 m s ==
rev. 0.1 /mar 2009 63 h5tq2g43bmr-xxc h5tq2g83bmr-xxc although for slow slew rates the total setup time might be negative (i.e. a valid input si gnal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input si gnal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in table 2, the derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by design and characterization. table 1 ? add/cmd setup and hold base-values for 1v/ns note: - (ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) - the tis (base) ac150 specifications are adjusted from the tis (base) specification by adding an additional 100 ps of derating to accommodate for the lo wer alternate threshold of 150 mv and another 25 ps to account for the ear lier reference point [(175 mv - 150 mv) / 1 v/ns] unit [ps] ddr3-1066 ddr3-1333 reference tis (base) 125 65 v ih/l(ac) tih (base) 200 140 v ih/l(dc) tih(base)ac150 - 65 + 125 v ih/l(dc)
rev. 0.1 /mar 2009 64 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 2 ? derating values ddr3-1066/1333 tis/tih - ac/dc based table 3 ? derating values ddr3-1066/1333 tis/tih - ac/dc based ? tis, ? tih derating in [ps] ac/dc based ac175 threshold -> vih (ac) = vref (dc) + 175mv, vil (ac) = vref (dc) - 175mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd / add slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.55934593459 34 67427550835891689984 1.00 0 0 0 0 0 8 8 1616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412222030303846 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 ? tis, ? tih derating in [ps] ac/dc based alternate ac150 threshold -> vih (ac) = vref (dc) + 150mv, vil (ac) = vref (dc) - 150mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd / add slew rate v/ns 2.07550755075 50 83589166997410784115100 1.55034503450 34 58426650745882689084 1.00 0 0 0 0 0 8 8 1616242432344050 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10
rev. 0.1 /mar 2009 65 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 4 ? required time t vac above vih (ac) {below vil (ac)} for valid transition slew rate [v/ns] t vac @ 175 mv [ps] t vac @ 150 mv [ps] minmaxminmax > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 -
rev. 0.1 /mar 2009 66 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 1 ? illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - v il(ac) max ? tf = v ih(ac) min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 67 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 2 ? illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - v il(dc) max ? tr = v ih(dc) min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 68 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 3 ? illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v ss tdh setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line [ v ref(dc) - v il(ac) max] ? tf = tangent line [v ih(ac) min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 69 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 4 ? illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v ss hold slew rate ? tf ? tr tangent line [v ih(dc) min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] ? tr = rising signal tdh tds dqs dqs tdh tds ck tis tih tis tih n o t e: cl oc k an d st ro b e are d rawn on a different time scale. ck
rev. 0.1 /mar 2009 70 h5tq2g43bmr-xxc h5tq2g83bmr-xxc data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is ca lculated by adding the data sheet tds (base) and tdh (base) value (see table 5) to the dtds and dtdh (see table 6) derating value respectively. example: tds (total setup time) = tds (base) + dtds. setup (tds) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tds) nominal slew rate for a falling sign al is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac) max (see figure 5). if the actual sign al is always earlier than the nomi- nal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc le vel is used for derating value (see figure 7). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc) min and the first crossing of v ref(dc) (see figure 6). if the actual signal is al ways later than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for dera ting value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 7). for a valid transition the input si gnal has to remain above/below v ih/il(ac) for some time t vac (see table 7). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input sign al is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifi ed by design and characterization. table 5 ? data setup and hold base-values note: (ac/dc referenced for 1v/ns dq-sle w rate and 2 v/ns dqs-slew rate) units [ps] ddr3-1066 ddr3-1333 reference tds (base) 25 -10 v ih/l(ac) tdh (base) 100 65 v ih/l(dc)
rev. 0.1 /mar 2009 71 h5tq2g43bmr-xxc h5tq2g83bmr-xxc table 6 ? derating values ddr3-1066 tds/tdh - ac/dc based table 7 ? required time t vac above vih (ac) {below vil (ac)} for valid transition ? tds, ? dh derating in [ps] ac/dc based a a.cell contents shaded in red are defined as ?not supported?. dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq slew rate v/ns 2.08850885088 50 - - - - - - - - - - 1.55934593459 346742 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21182934 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - --11-16-2-6 510 0.4 - - - - - - - - - - - - -30 -26 -22 -10 slew rate [v/ns] t vac [ps] min max > 2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - < 0.5 0 -
rev. 0.1 /mar 2009 72 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 5 ? illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - v il(ac) max ? tf = v ih(ac) min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 73 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 6 ? illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - v il(dc) max ? tr = v ih(dc) min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 74 h5tq2g43bmr-xxc h5tq2g83bmr-xxc figure 7 ? illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/ cmd with respect to clock) v ss tdh setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line [ v ref(dc) - v il(ac) max] ? tf = tangent line [v ih(ac) min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 75 figure 8 ? illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/ cmd with respect to clock) v ss hold slew rate ? tf ? tr tangent line [v ih(dc) min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] ? tr = rising signal tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale.
rev. 0.1 /mar 2009 76 h5tq2g43bmr-xxc h5tq2g83bmr-xxc 12. package dimensions 12.1 package dimension(x4/x 8); 78ball fine pitch ball grid array outline a1 corner index area (2.750) (1.975) 7.900 0.100 11.000 0.100 0.290 0.050 1.250 0.100 987 321 a b c d e f g h j k l m n 0.750 0.100 2.100 0.100 0.800 x 8 = 6.400 0.800 a1 ball mark 1.600 0.800 x 12 = 9.600 0.800 1.600 78 x 0.400 0.050 0.750 0.100 0.150 0.050 2-r0.130 max top view bottom view side view 3.0 x 5.0 min flat area

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